The present invention relates to an apparatus for translating virtual addresses stored in a virtual storage to physical addresses and, more particularly, to an address translation apparatus which permits plural processes to share an address translation entry. The invention also relates to a computer system including this address translation apparatus.
A virtual storage method has been widely adopted as a technique for reducing the load on programming, against the limit of the capacity of a main memory in a computer. In the virtual storage, a large-capacity virtual memory is created by controlling a main memory and an auxiliary memory (e.g., a hard disk) so as to supplement the memory capacity by using an operation system or the like, thereby logically realizing a large-capacity main memory. Further, when adopting the virtual storage, only the data required for activating a program can be stored in the main memory, plural programs can share the memory with high efficiency.
In the virtual storage, it is necessary to translate virtual addresses indicating addresses in the virtual memory, to physical addresses indicating addresses in the actual main memory.
Generally, a virtual address is separable into a virtual page number and an in-page offset, and also a physical address is separable into a physical page number and an in-page offset. In address translation, a page table in which virtual page numbers are associated with the corresponding physical page numbers is prepared in advance, and a physical page number is extracted from a requested virtual address with reference to this page table, thereby translating the virtual address to the physical address. Since the in-page offset of the virtual address is equal to that of the corresponding physical address, a physical address is generated by connecting a predetermined in-page offset to the physical page number.
By the way, since the page table is very large in size, it must be stored in the main memory. Accordingly, every time a request for access to the main memory is output from a CPU, two accesses (i.e., access to the page table and access to the actual data) are made to the main memory, thereby generating a delay in processing time. In order to avoid such delay in processing time, recently a translation look-aside buffer (hereinafter referred to as xe2x80x9cTLBxe2x80x9d) has been used in addition to the page table.
The TLB is a cash memory for address translation only, in which virtual page numbers of high frequency and the corresponding physical page numbers are stored, amongst those stored in the page table. When the CPU accesses the main memory, the TLB is searched first, and only when the desired virtual address is not stored in the TLB, the page table is searched. By appropriately setting the contents of the TLB to increase the hit ratio of the TLB, highly efficient access to the main memory is realized.
Hereinafter, the structure of the TLB will be described in brief. The TLB has a plurality of entries, and each entry contains a virtual page number, a physical page number, and a process identifier composed of plural bits. Therefore, when an entry is referred to, a virtual page number and a corresponding physical page number are known. Each entry is separated into a tag section and a data section. The tag section is composed of a virtual page number, a process identifier indicating a process, a global bit which defines as to whether the process identifier should be referred to or not, and the like. The data section is composed of a physical page number and the like.
The purpose of giving the process identifier is to prevent the virtual addresses from being confused due to coexistence of different processes.
To be specific, a plurality of processes, which are simultaneously executed by a computer, share a TLB, and each process can independently set a virtual address space. So, the virtual addresses used by the respective processes may overlap, and there may occur plural entries in which the same vertical page number corresponds to different physical page numbers. Therefore, in principle, a process identifier is given to each entry, and a physical address is extracted from an entry in which the process identifier is equal to the process identifier of a process which requires a virtual address, whereby error address translation is avoided and memory protection is achieved amongst the processes.
Further, also in the case where two or more different processes use the same virtual address corresponding to the same physical address, when a specific process is being executed and therefore the other process should not make access to this physical address, decision is made by using the process identifiers of these processes.
On the other hand, when there is a physical address which can be shared among plural processes, the same virtual address corresponding to this physical address is used for each of the respective process identifiers, whereby the entries which are to be provided process by process are grouped to reduce the number of entries corresponding to the same virtual address. Thus, the memory area of the TLB having a relatively small memory capacity can be used with efficiency.
Further, the hit ratio of the TLB can be increased by storing more entries in a vacant space which is made as the result of the sharing.
Since address translation is performed using the virtual page number alone when plural processes share an entry, each entry is provided with a global bit (one bit) which defines as to whether the process identifier should be referred to or not. When an entry is shared among plural processes, its global bit is made active so as not to ask about matching of process identifiers. Since matching of process identifiers is not decided when the global bit is active, an entry the global bit of which is active is shared amongst all the processes.
When the TLB so constructed receives a request for an virtual address from the CPU, an entry which contains a virtual page number constituting this virtual address is retrieved. To be specific, when the global bit is inactive (xe2x80x9c0xe2x80x9d), an entry having the same process identifier as that of the currently executed process is retrieved. On the other hand, when the global bit is active (xe2x80x9c1xe2x80x9d), an entry the virtual page number of which is equal to that of the requested virtual address is retrieved without regard to matching of process identifiers. When there is an entry that satisfies the condition, a translation hit signal is output to the CPU, and the physical page number stored in this entry is translated to a physical address to be sent to the CPU.
By the way, for the sake of memory protection, it is impossible to permit all processes in a physical memory to share a physical address relating to a certain content stored in the physical memory. However, depending on the contents of the programs, some of these processes may share the physical address. However, in the conventional TLB, because of its construction, all the processes cannot but share the physical address. Therefore, even when plural processes which can share the physical address are included in the physical memory, the entries relating to these processes cannot be unified, and an entry corresponding to each process should be formed for the sake of memory protection. That is, when there is a physical address which can be shared among some processes as described above, the memory area of the TLB is wastefully used with respect to the group of these processes.
Further, if the entries are unified such that all of the processes can share a physical address for effective utilization of the memory area, some processes which should not use the physical address can make access to this physical access. As the result, memory protection is not achieved.
The present invention is made to solve the above-described problems and has for its object to provide an address translation apparatus which can effectively utilize a memory area and achieve memory protection by unifying entries with respect to some processes which are permitted to share a content stored in a physical memory.
It is another object of the present invention to provide a computer system having this address translation apparatus.
Other objects and advantages of the invention will become apparent from the detailed description that follows. The detailed description and specific embodiments described are provided only for illustration since various additions and modifications within the scope of the invention will be apparent to those of skill in the art from the detailed description.
According to a first aspect of the present invention, there is provided an address translation apparatus comprising: entry storage means for storing a plurality of entries, each entry containing a virtual page number, a physical page number, and a process identifier which is composed of plural bits; comparison information storage means for storing comparison information which defines a method for comparing a process identifier possessed by a process that is currently executed, with the process identifier in each entry; process comparison means for comprising the process identifier possessed by the process that is currently executed, with the process identifier in the entry, on the basis of the comparison information; and entry retrieval means for retrieving, from the entry storage means, an entry including a virtual page number equal to a virtual page number supplied from the outside, and a process identifier which matches the process identifier of the currently executed process, according to the result of the comparison by the process comparison means.
According to a second aspect of the present invention, in the above-described address translation apparatus, each entry is provided with the comparison information storage means, and the comparison information is global bits.
According to a third aspect of the present invention, in the above-described address translation apparatus, the comparison information defines at least two kinds of comparison methods, and one of the comparison methods is a method for comparing part of plural bits constituting the process identifier possessed by the currently executed process, with the corresponding part of plural bits constituting the process identifier of the entry.
According to a fourth aspect of the present invention, there is provided a computer system having the above-described address translation apparatus.